Verification

In the preceding section, we discussed how to construct a verification Taproot for validating a single logic gate. In this section, we will delve into extending the script for verifying a single logic gate to the entire circuit. We will employ a simple principle: the output of each logic gate serves as the input to the next logic gate.

In the diagram below, (4) receives the output of gate B and acts as the input to gate C. Assuming that the output of gate B does not match the input of gate C, it implies that (4) has two possible values, which is evidently incorrect. By using the script provided earlier, we can ensure the correctness of both the input and output of gate B and also verify the input and output of gate C. Next, by leveraging the property that the input equals the output of (4), it suffices to validate that the output of gate B equals the input of gate C to ensure the overall correctness of the two logic gates formed by gate B and gate C. By extension, we can ultimately prove the correctness of the entire circuit.

If the Prover violates this rule, we can easily identify issues within the circuit. As shown in the diagram below, if the Prover assigns different values to (4), the Verifier can readily detect this problem and declare the entire circuit invalid.

In summary, the Verifier constructs all possible scenarios of logic gate malfunctions within the Verification Taproot. The Verifier only needs to detect a single logic gate malfunction off-chain to construct a spending Taproot unlocking script. Clearly, this is a non-interactive approach.